At the Semico Impact Conference: Focus on the IP Ecosystem, Mahesh Tirupattur, Executive Vice President, Analog Bits, challenged four panelists to an engaging discussion on their approach to IP Ecosystem Solutions for Complex Systems. Panel participants included Dan Kochpatcharin, Deputy Director, IP Portfolio Management, TSMC; Jason Polychronopoulos, Mentor Graphics; Chris Rowen, Cadence Fellow; and Warren Savage, President and CEO, IPextreme.
Tirupattur skillfully pulled both humorous and discriminating observations from the foundry perspective, the EDA perspective and both a large and small IP vendor.
The topic of the panel was the high cost and risk of integrating IP in today’s semiconductor product development. There’s a massive risk of product failure from choosing the wrong IP, the wrong supplier, the wrong fab, or the wrong process. A misstep means jobs could be on the line. Today, complex SoCs are not comprised of just one or two IP blocks, it’s a battalion of IP coming from a variety of sources. Dan Kochpatcharin of TSMC noted that at the 20nm node an average design has 12 unique IP blocks. That compares to an average of only eight at the 28nm node.
